Field of the Invention
The invention relates to a method for accelerated access to signals of a programmable logic device at run time, a device for accessing signals of a programmable logic device, and a computer program product.
Description of the Background Art
For the control or simulation of dynamic systems, increasing use is being made of rapid control prototyping systems and hardware-in-the-loop simulators that have one or more programmable logic devices known, for example, Field Programmable Gate Arrays (FPGA) in addition to the microprocessors that are generally present. One example of a simulation of a dynamic system by means of an FPGA is known from the article, “All Under One Roof,” pp. 48-51, dSPACE Magazine March 2009, available at www.dspace.com. At its functional level, an FPGA includes a plurality of logic elements and connecting elements, the precise interconnection of which is only defined at initialization by means of a bit stream that is written into the configuration level of the device. The architecture of FPGAs thus allows for good matching to the specific application and parallel processing of signals, so that FPGAs can also reliably simulate or control rapidly changing controlled systems.
The configuration of an FPGA described by the bit stream can be created, with the aid of a block diagram of the system to be modeled, as is described, for example, in the article, “Speed and Flexibility FPGA,” pages 40-43, dSPACE Magazine March 2009. This permits convenient operation for the user, but requires a comparatively great expenditure of time due to the intermediate steps required. During analysis of the system or controller, it may frequently be necessary to access certain signals in the model in order to determine the current output value of a block under consideration, for example. In useful fashion, it should thus be possible to access various signal values of an FPGA, without changing the configuration, while it is executing a configuration corresponding to the model. A corresponding method for accessing a signal value of an FPGA at run time is known from DE 10 2013 101 300 A1, which is incorporated herein by reference.
Access to the signal values takes place here through the configuration level of the FPGA, which has a multiplicity of address ranges or address units by means of which memory elements can be addressed. In order to limit the size and complexity of the address logic, the address units of commercial FPGAs include a multiplicity of words or a correspondingly larger number of bits. Even if access to only a single bit is requested, all words from the start of the address unit to the requested bit must be read. Consequently, only a small number of signals can be measured during the simulation of a dynamic system on account of the limited speed of access to the configuration level.
From U.S. Pat. No. 7,271,616 B2 is known an improved circuit arrangement for reducing readback time of an FPGA. However, this circuit requires modifications to the programmable logic device itself, and thus is only available to a manufacturer of applicable devices.